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authorIndrajith K L2022-12-03 17:00:20 +0530
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tree2764fc62da58f2ba8da7ed341643fc359873142f /ctags/man/ctags-lang-verilog.7.html
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+<body>
+<div class="document" id="ctags-lang-verilog">
+<span id="ctags-lang-verilog-7"></span>
+<h1 class="title">ctags-lang-verilog</h1>
+<h2 class="subtitle" id="the-man-page-about-systemverilog-verilog-parser-for-universal-ctags">The man page about SystemVerilog/Verilog parser for Universal Ctags</h2>
+<table class="docinfo" frame="void" rules="none">
+<col class="docinfo-name" />
+<col class="docinfo-content" />
+<tbody valign="top">
+<tr><th class="docinfo-name">Version:</th>
+<td>5.9.0</td></tr>
+<tr class="manual-group field"><th class="docinfo-name">Manual group:</th><td class="field-body">Universal Ctags</td>
+</tr>
+<tr class="manual-section field"><th class="docinfo-name">Manual section:</th><td class="field-body">7</td>
+</tr>
+</tbody>
+</table>
+<div class="section" id="synopsis">
+<h1>SYNOPSIS</h1>
+<div class="line-block">
+<div class="line"><strong>ctags</strong> ... [--kinds-systemverilog=+Q] [--fields-SystemVerilog=+{parameter}] ...</div>
+<div class="line"><strong>ctags</strong> ... [--fields-Verilog=+{parameter}] ...</div>
+</div>
+<blockquote>
+<table border="1" class="docutils">
+<colgroup>
+<col width="31%" />
+<col width="31%" />
+<col width="39%" />
+</colgroup>
+<thead valign="bottom">
+<tr><th class="head">Language</th>
+<th class="head">Language ID</th>
+<th class="head">File Mapping</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr><td>SystemVerilog</td>
+<td>SystemVerilog</td>
+<td>.sv, .svh, svi</td>
+</tr>
+<tr><td>Verilog</td>
+<td>Verilog</td>
+<td>.v</td>
+</tr>
+</tbody>
+</table>
+</blockquote>
+</div>
+<div class="section" id="description">
+<h1>DESCRIPTION</h1>
+<p>This man page describes about the SystemVerilog/Verilog parser for Universal Ctags.
+SystemVerilog parser supports IEEE Std 1800-2017 keywords.
+Verilog parser supports IEEE Std 1364-2005 keywords.</p>
+<div class="section" id="supported-kinds">
+<h2>Supported Kinds</h2>
+<pre class="code console literal-block">
+<span class="generic prompt">$ </span>ctags --list-kinds-full<span class="operator">=</span>SystemVerilog
+<span class="generic prompt">#</span>LETTER NAME ENABLED REFONLY NROLES MASTER DESCRIPTION
+<span class="generic output">A assert yes no 0 NONE assertions (assert, assume, cover, restrict)
+C class yes no 0 NONE classes
+E enum yes no 0 NONE enumerators
+H checker yes no 0 NONE checkers
+I interface yes no 0 NONE interfaces
+K package yes no 0 NONE packages
+L clocking yes no 0 NONE clocking
+M modport yes no 0 NONE modports
+N nettype yes no 0 NONE nettype declarations
+O constraint yes no 0 NONE constraints
+P program yes no 0 NONE programs
+Q prototype no no 0 NONE prototypes (extern, pure)
+R property yes no 0 NONE properties
+S struct yes no 0 NONE structs and unions
+T typedef yes no 0 NONE type declarations
+V covergroup yes no 0 NONE covergroups
+b block yes no 0 NONE blocks (begin, fork)
+c constant yes no 0 NONE constants (define, parameter, specparam, enum values)
+e event yes no 0 NONE events
+f function yes no 0 NONE functions
+i instance yes no 0 NONE instances of module or interface
+l ifclass yes no 0 NONE interface class
+m module yes no 0 NONE modules
+n net yes no 0 NONE net data types
+p port yes no 0 NONE ports
+q sequence yes no 0 NONE sequences
+r register yes no 0 NONE variable data types
+t task yes no 0 NONE tasks
+w member yes no 0 NONE struct and union members</span>
+</pre>
+<p>Note that <tt class="docutils literal">prototype</tt> (<tt class="docutils literal">Q</tt>) is disabled by default.</p>
+<pre class="code console literal-block">
+<span class="generic prompt">$ </span>ctags --list-kinds-full<span class="operator">=</span>Verilog
+<span class="generic prompt">#</span>LETTER NAME ENABLED REFONLY NROLES MASTER DESCRIPTION
+<span class="generic output">b block yes no 0 NONE blocks (begin, fork)
+c constant yes no 0 NONE constants (define, parameter, specparam)
+e event yes no 0 NONE events
+f function yes no 0 NONE functions
+i instance yes no 0 NONE instances of module
+m module yes no 0 NONE modules
+n net yes no 0 NONE net data types
+p port yes no 0 NONE ports
+r register yes no 0 NONE variable data types
+t task yes no 0 NONE tasks</span>
+</pre>
+</div>
+<div class="section" id="supported-language-specific-fields">
+<h2>Supported Language Specific Fields</h2>
+<pre class="code console literal-block">
+<span class="generic prompt">$ </span>ctags --list-fields<span class="operator">=</span>Verilog
+<span class="generic prompt">#</span>LETTER NAME ENABLED LANGUAGE JSTYPE FIXED DESCRIPTION
+<span class="generic output">- parameter no Verilog --b no parameter whose value can be overridden.
+</span><span class="generic prompt">$ </span>ctags --list-fields<span class="operator">=</span>SystemVerilog
+<span class="generic prompt">#</span>LETTER NAME ENABLED LANGUAGE JSTYPE FIXED DESCRIPTION
+<span class="generic output">- parameter no SystemVerilog --b no parameter whose value can be overridden.</span>
+</pre>
+<div class="section" id="parameter-field">
+<h3><tt class="docutils literal">parameter</tt> field</h3>
+<p>If the field <tt class="docutils literal">parameter</tt> is enabled, a field <tt class="docutils literal">parameter:</tt> is added on a parameter whose
+value can be overridden on an instantiated module, interface, or program.
+This is useful for a editor plugin or extension to enable auto-instantiation of modules with
+parameters which can be overridden.</p>
+<pre class="code console literal-block">
+<span class="generic prompt">$ </span>ctags ... --fields-Verilog<span class="operator">=</span>+<span class="operator">{</span>parameter<span class="operator">}</span> ...
+<span class="generic prompt">$ </span>ctags ... --fields-SystemVerilog<span class="operator">=</span>+<span class="operator">{</span>parameter<span class="operator">}</span> ...
+</pre>
+<p>On the following source code fields <tt class="docutils literal">parameter:</tt> are added on
+parameters <tt class="docutils literal">P*</tt>, not on ones <tt class="docutils literal">L*</tt>. Note that <tt class="docutils literal">L4</tt> and <tt class="docutils literal">L6</tt> is declared by
+<tt class="docutils literal">parameter</tt> statement, but fields <tt class="docutils literal">parameter:</tt> are not added,
+because they cannot be overridden.</p>
+<p>&quot;input.sv&quot;</p>
+<pre class="code systemverilog literal-block">
+<span class="comment single">// compilation unit scope
+</span><span class="keyword">parameter</span> <span class="name">L1</span> <span class="operator">=</span> <span class="literal string">&quot;synonym for the localparam&quot;</span><span class="punctuation">;</span>
+
+<span class="keyword">module</span> <span class="name">with_parameter_port_list</span> <span class="punctuation">#(</span>
+ <span class="name">P1</span><span class="punctuation">,</span>
+ <span class="keyword">localparam</span> <span class="name">L2</span> <span class="operator">=</span> <span class="name">P1</span><span class="operator">+</span><span class="literal number integer">1</span><span class="punctuation">,</span>
+ <span class="keyword">parameter</span> <span class="name">P2</span><span class="punctuation">)</span>
+ <span class="punctuation">(</span> <span class="comment multiline">/*port list...*/</span> <span class="punctuation">);</span>
+ <span class="keyword">parameter</span> <span class="name">L3</span> <span class="operator">=</span> <span class="literal string">&quot;synonym for the localparam&quot;</span><span class="punctuation">;</span>
+ <span class="keyword">localparam</span> <span class="name">L4</span> <span class="operator">=</span> <span class="literal string">&quot;localparam&quot;</span><span class="punctuation">;</span>
+ <span class="comment single">// ...
+</span><span class="keyword">endmodule</span>
+
+<span class="keyword">module</span> <span class="name">with_empty_parameter_port_list</span> <span class="punctuation">#()</span>
+ <span class="punctuation">(</span> <span class="comment multiline">/*port list...*/</span> <span class="punctuation">);</span>
+ <span class="keyword">parameter</span> <span class="name">L5</span> <span class="operator">=</span> <span class="literal string">&quot;synonym for the localparam&quot;</span><span class="punctuation">;</span>
+ <span class="keyword">localparam</span> <span class="name">L6</span> <span class="operator">=</span> <span class="literal string">&quot;localparam&quot;</span><span class="punctuation">;</span>
+ <span class="comment single">// ...
+</span><span class="keyword">endmodule</span>
+
+<span class="keyword">module</span> <span class="name">no_parameter_port_list</span>
+ <span class="punctuation">(</span> <span class="comment multiline">/*port list...*/</span> <span class="punctuation">);</span>
+ <span class="keyword">parameter</span> <span class="name">P3</span> <span class="operator">=</span> <span class="literal string">&quot;parameter&quot;</span><span class="punctuation">;</span>
+ <span class="keyword">localparam</span> <span class="name">L7</span> <span class="operator">=</span> <span class="literal string">&quot;localparam&quot;</span><span class="punctuation">;</span>
+ <span class="comment single">// ...
+</span><span class="keyword">endmodule</span>
+</pre>
+<pre class="code console literal-block">
+<span class="generic prompt">$ </span>ctags -uo - --fields-SystemVerilog<span class="operator">=</span>+<span class="operator">{</span>parameter<span class="operator">}</span> input.sv
+<span class="generic output">L1 input.sv /^parameter L1 = &quot;synonym for the localparam&quot;;$/;&quot; c parameter:
+with_parameter_port_list input.sv /^module with_parameter_port_list #($/;&quot; m
+P1 input.sv /^ P1,$/;&quot; c module:with_parameter_port_list parameter:
+L2 input.sv /^ localparam L2 = P1+1,$/;&quot; c module:with_parameter_port_list
+P2 input.sv /^ parameter P2)$/;&quot; c module:with_parameter_port_list parameter:
+L3 input.sv /^ parameter L3 = &quot;synonym for the localparam&quot;;$/;&quot; c module:with_parameter_port_list
+L4 input.sv /^ localparam L4 = &quot;localparam&quot;;$/;&quot; c module:with_parameter_port_list
+with_empty_parameter_port_list input.sv /^module with_empty_parameter_port_list #()$/;&quot; m
+L5 input.sv /^ parameter L5 = &quot;synonym for the localparam&quot;;$/;&quot; c module:with_empty_parameter_port_list
+L6 input.sv /^ localparam L6 = &quot;localparam&quot;;$/;&quot; c module:with_empty_parameter_port_list
+no_parameter_port_list input.sv /^module no_parameter_port_list$/;&quot; m
+P3 input.sv /^ parameter P3 = &quot;parameter&quot;;$/;&quot; c module:no_parameter_port_list parameter:
+L7 input.sv /^ localparam L7 = &quot;localparam&quot;;$/;&quot; c module:no_parameter_port_list</span>
+</pre>
+</div>
+</div>
+<div class="section" id="tips">
+<h2>TIPS</h2>
+<p>If you want to map files <tt class="docutils literal">*.v</tt> to SystemVerilog, add
+<tt class="docutils literal"><span class="pre">--langmap=SystemVerilog:.v</span></tt> option.</p>
+</div>
+</div>
+<div class="section" id="known-issues">
+<h1>KNOWN ISSUES</h1>
+<p>See <a class="reference external" href="https://github.com/universal-ctags/ctags/issues/2674">https://github.com/universal-ctags/ctags/issues/2674</a> for more information.</p>
+</div>
+<div class="section" id="see-also">
+<h1>SEE ALSO</h1>
+<ul class="simple">
+<li>ctags(1)</li>
+<li>ctags-client-tools(7)</li>
+<li><dl class="first docutils">
+<dt>Language Reference Manuals (LRM)</dt>
+<dd><ul class="first last">
+<li>IEEE Standard for SystemVerilog — Unified Hardware Design, Specification, and
+Verification Language, IEEE Std 1800-2017,
+<a class="reference external" href="https://ieeexplore.ieee.org/document/8299595">https://ieeexplore.ieee.org/document/8299595</a></li>
+<li>IEEE Standard for Verilog Hardware Description Language, IEEE Std 1364-2005,
+<a class="reference external" href="https://ieeexplore.ieee.org/document/1620780">https://ieeexplore.ieee.org/document/1620780</a></li>
+</ul>
+</dd>
+</dl>
+</li>
+</ul>
+</div>
+</div>
+</body>
+</html>