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diff --git a/ctags/docs/man/ctags-lang-verilog.7.html b/ctags/docs/man/ctags-lang-verilog.7.html new file mode 100644 index 0000000..2114fac --- /dev/null +++ b/ctags/docs/man/ctags-lang-verilog.7.html @@ -0,0 +1,318 @@ + +<!DOCTYPE html> + +<html> + <head> + <meta charset="utf-8" /> + <meta name="viewport" content="width=device-width, initial-scale=1.0" /><meta name="generator" content="Docutils 0.17.1: http://docutils.sourceforge.net/" /> + + <title>ctags-lang-verilog — Universal Ctags 0.3.0 documentation</title> + <link rel="stylesheet" type="text/css" href="../_static/pygments.css" /> + <link rel="stylesheet" type="text/css" href="../_static/classic.css" /> + + <script data-url_root="../" id="documentation_options" src="../_static/documentation_options.js"></script> + <script src="../_static/jquery.js"></script> + <script src="../_static/underscore.js"></script> + <script src="../_static/doctools.js"></script> + + <link rel="index" title="Index" href="../genindex.html" /> + <link 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class="document"> + <div class="documentwrapper"> + <div class="bodywrapper"> + <div class="body" role="main"> + + <section id="ctags-lang-verilog"> +<span id="ctags-lang-verilog-7"></span><h1>ctags-lang-verilog<a class="headerlink" href="#ctags-lang-verilog" title="Permalink to this headline">¶</a></h1> +<p>The man page about SystemVerilog/Verilog parser for Universal Ctags</p> +<dl class="field-list simple"> +<dt class="field-odd">Version</dt> +<dd class="field-odd"><p>5.9.0</p> +</dd> +<dt class="field-even">Manual group</dt> +<dd class="field-even"><p>Universal Ctags</p> +</dd> +<dt class="field-odd">Manual section</dt> +<dd class="field-odd"><p>7</p> +</dd> +</dl> +<section id="synopsis"> +<h2>SYNOPSIS<a class="headerlink" href="#synopsis" title="Permalink to this headline">¶</a></h2> +<div class="line-block"> +<div class="line"><strong>ctags</strong> … [--kinds-systemverilog=+Q] [--fields-SystemVerilog=+{parameter}] …</div> +<div class="line"><strong>ctags</strong> … [--fields-Verilog=+{parameter}] …</div> +</div> +<blockquote> +<div><table class="docutils align-default"> +<colgroup> +<col style="width: 31%" /> +<col style="width: 31%" /> +<col style="width: 39%" /> +</colgroup> +<thead> +<tr class="row-odd"><th class="head"><p>Language</p></th> +<th class="head"><p>Language ID</p></th> +<th class="head"><p>File Mapping</p></th> +</tr> +</thead> +<tbody> +<tr class="row-even"><td><p>SystemVerilog</p></td> +<td><p>SystemVerilog</p></td> +<td><p>.sv, .svh, svi</p></td> +</tr> +<tr class="row-odd"><td><p>Verilog</p></td> +<td><p>Verilog</p></td> +<td><p>.v</p></td> +</tr> +</tbody> +</table> +</div></blockquote> +</section> +<section id="description"> +<h2>DESCRIPTION<a class="headerlink" href="#description" title="Permalink to this headline">¶</a></h2> +<p>This man page describes about the SystemVerilog/Verilog parser for Universal Ctags. +SystemVerilog parser supports IEEE Std 1800-2017 keywords. +Verilog parser supports IEEE Std 1364-2005 keywords.</p> +<section id="supported-kinds"> +<h3>Supported Kinds<a class="headerlink" href="#supported-kinds" title="Permalink to this headline">¶</a></h3> +<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="gp">$ </span>ctags --list-kinds-full<span class="o">=</span>SystemVerilog +<span class="gp">#</span>LETTER NAME ENABLED REFONLY NROLES MASTER DESCRIPTION +<span class="go">A assert yes no 0 NONE assertions (assert, assume, cover, restrict)</span> +<span class="go">C class yes no 0 NONE classes</span> +<span class="go">E enum yes no 0 NONE enumerators</span> +<span class="go">H checker yes no 0 NONE checkers</span> +<span class="go">I interface yes no 0 NONE interfaces</span> +<span class="go">K package yes no 0 NONE packages</span> +<span class="go">L clocking yes no 0 NONE clocking</span> +<span class="go">M modport yes no 0 NONE modports</span> +<span class="go">N nettype yes no 0 NONE nettype declarations</span> +<span class="go">O constraint yes no 0 NONE constraints</span> +<span class="go">P program yes no 0 NONE programs</span> +<span class="go">Q prototype no no 0 NONE prototypes (extern, pure)</span> +<span class="go">R property yes no 0 NONE properties</span> +<span class="go">S struct yes no 0 NONE structs and unions</span> +<span class="go">T typedef yes no 0 NONE type declarations</span> +<span class="go">V covergroup yes no 0 NONE covergroups</span> +<span class="go">b block yes no 0 NONE blocks (begin, fork)</span> +<span class="go">c constant yes no 0 NONE constants (define, parameter, specparam, enum values)</span> +<span class="go">e event yes no 0 NONE events</span> +<span class="go">f function yes no 0 NONE functions</span> +<span class="go">i instance yes no 0 NONE instances of module or interface</span> +<span class="go">l ifclass yes no 0 NONE interface class</span> +<span class="go">m module yes no 0 NONE modules</span> +<span class="go">n net yes no 0 NONE net data types</span> +<span class="go">p port yes no 0 NONE ports</span> +<span class="go">q sequence yes no 0 NONE sequences</span> +<span class="go">r register yes no 0 NONE variable data types</span> +<span class="go">t task yes no 0 NONE tasks</span> +<span class="go">w member yes no 0 NONE struct and union members</span> +</pre></div> +</div> +<p>Note that <code class="docutils literal notranslate"><span class="pre">prototype</span></code> (<code class="docutils literal notranslate"><span class="pre">Q</span></code>) is disabled by default.</p> +<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="gp">$ </span>ctags --list-kinds-full<span class="o">=</span>Verilog +<span class="gp">#</span>LETTER NAME ENABLED REFONLY NROLES MASTER DESCRIPTION +<span class="go">b block yes no 0 NONE blocks (begin, fork)</span> +<span class="go">c constant yes no 0 NONE constants (define, parameter, specparam)</span> +<span class="go">e event yes no 0 NONE events</span> +<span class="go">f function yes no 0 NONE functions</span> +<span class="go">i instance yes no 0 NONE instances of module</span> +<span class="go">m module yes no 0 NONE modules</span> +<span class="go">n net yes no 0 NONE net data types</span> +<span class="go">p port yes no 0 NONE ports</span> +<span class="go">r register yes no 0 NONE variable data types</span> +<span class="go">t task yes no 0 NONE tasks</span> +</pre></div> +</div> +</section> +<section id="supported-language-specific-fields"> +<h3>Supported Language Specific Fields<a class="headerlink" href="#supported-language-specific-fields" title="Permalink to this headline">¶</a></h3> +<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="gp">$ </span>ctags --list-fields<span class="o">=</span>Verilog +<span class="gp">#</span>LETTER NAME ENABLED LANGUAGE JSTYPE FIXED DESCRIPTION +<span class="go">- parameter no Verilog --b no parameter whose value can be overridden.</span> +<span class="gp">$ </span>ctags --list-fields<span class="o">=</span>SystemVerilog +<span class="gp">#</span>LETTER NAME ENABLED LANGUAGE JSTYPE FIXED DESCRIPTION +<span class="go">- parameter no SystemVerilog --b no parameter whose value can be overridden.</span> +</pre></div> +</div> +<section id="parameter-field"> +<h4><code class="docutils literal notranslate"><span class="pre">parameter</span></code> field<a class="headerlink" href="#parameter-field" title="Permalink to this headline">¶</a></h4> +<p>If the field <code class="docutils literal notranslate"><span class="pre">parameter</span></code> is enabled, a field <code class="docutils literal notranslate"><span class="pre">parameter:</span></code> is added on a parameter whose +value can be overridden on an instantiated module, interface, or program. +This is useful for a editor plugin or extension to enable auto-instantiation of modules with +parameters which can be overridden.</p> +<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="gp">$ </span>ctags ... --fields-Verilog<span class="o">=</span>+<span class="o">{</span>parameter<span class="o">}</span> ... +<span class="gp">$ </span>ctags ... --fields-SystemVerilog<span class="o">=</span>+<span class="o">{</span>parameter<span class="o">}</span> ... +</pre></div> +</div> +<p>On the following source code fields <code class="docutils literal notranslate"><span class="pre">parameter:</span></code> are added on +parameters <code class="docutils literal notranslate"><span class="pre">P*</span></code>, not on ones <code class="docutils literal notranslate"><span class="pre">L*</span></code>. Note that <code class="docutils literal notranslate"><span class="pre">L4</span></code> and <code class="docutils literal notranslate"><span class="pre">L6</span></code> is declared by +<code class="docutils literal notranslate"><span class="pre">parameter</span></code> statement, but fields <code class="docutils literal notranslate"><span class="pre">parameter:</span></code> are not added, +because they cannot be overridden.</p> +<p>“input.sv”</p> +<div class="highlight-systemverilog notranslate"><div class="highlight"><pre><span></span><span class="c1">// compilation unit scope</span> +<span class="k">parameter</span> <span class="n">L1</span> <span class="o">=</span> <span class="s">"synonym for the localparam"</span><span class="p">;</span> + +<span class="k">module</span> <span class="n">with_parameter_port_list</span> <span class="p">#(</span> + <span class="n">P1</span><span class="p">,</span> + <span class="k">localparam</span> <span class="n">L2</span> <span class="o">=</span> <span class="n">P1</span><span class="o">+</span><span class="mi">1</span><span class="p">,</span> + <span class="k">parameter</span> <span class="n">P2</span><span class="p">)</span> + <span class="p">(</span> <span class="cm">/*port list...*/</span> <span class="p">);</span> + <span class="k">parameter</span> <span class="n">L3</span> <span class="o">=</span> <span class="s">"synonym for the localparam"</span><span class="p">;</span> + <span class="k">localparam</span> <span class="n">L4</span> <span class="o">=</span> <span class="s">"localparam"</span><span class="p">;</span> + <span class="c1">// ...</span> +<span class="k">endmodule</span> + +<span class="k">module</span> <span class="n">with_empty_parameter_port_list</span> <span class="p">#()</span> + <span class="p">(</span> <span class="cm">/*port list...*/</span> <span class="p">);</span> + <span class="k">parameter</span> <span class="n">L5</span> <span class="o">=</span> <span class="s">"synonym for the localparam"</span><span class="p">;</span> + <span class="k">localparam</span> <span class="n">L6</span> <span class="o">=</span> <span class="s">"localparam"</span><span class="p">;</span> + <span class="c1">// ...</span> +<span class="k">endmodule</span> + +<span class="k">module</span> <span class="n">no_parameter_port_list</span> + <span class="p">(</span> <span class="cm">/*port list...*/</span> <span class="p">);</span> + <span class="k">parameter</span> <span class="n">P3</span> <span class="o">=</span> <span class="s">"parameter"</span><span class="p">;</span> + <span class="k">localparam</span> <span class="n">L7</span> <span class="o">=</span> <span class="s">"localparam"</span><span class="p">;</span> + <span class="c1">// ...</span> +<span class="k">endmodule</span> +</pre></div> +</div> +<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="gp">$ </span>ctags -uo - --fields-SystemVerilog<span class="o">=</span>+<span class="o">{</span>parameter<span class="o">}</span> input.sv +<span class="go">L1 input.sv /^parameter L1 = "synonym for the localparam";$/;" c parameter:</span> +<span class="go">with_parameter_port_list input.sv /^module with_parameter_port_list #($/;" m</span> +<span class="go">P1 input.sv /^ P1,$/;" c module:with_parameter_port_list parameter:</span> +<span class="go">L2 input.sv /^ localparam L2 = P1+1,$/;" c module:with_parameter_port_list</span> +<span class="go">P2 input.sv /^ parameter P2)$/;" c module:with_parameter_port_list parameter:</span> +<span class="go">L3 input.sv /^ parameter L3 = "synonym for the localparam";$/;" c module:with_parameter_port_list</span> +<span class="go">L4 input.sv /^ localparam L4 = "localparam";$/;" c module:with_parameter_port_list</span> +<span class="go">with_empty_parameter_port_list input.sv /^module with_empty_parameter_port_list #()$/;" m</span> +<span class="go">L5 input.sv /^ parameter L5 = "synonym for the localparam";$/;" c module:with_empty_parameter_port_list</span> +<span class="go">L6 input.sv /^ localparam L6 = "localparam";$/;" c module:with_empty_parameter_port_list</span> +<span class="go">no_parameter_port_list input.sv /^module no_parameter_port_list$/;" m</span> +<span class="go">P3 input.sv /^ parameter P3 = "parameter";$/;" c module:no_parameter_port_list parameter:</span> +<span class="go">L7 input.sv /^ localparam L7 = "localparam";$/;" c module:no_parameter_port_list</span> +</pre></div> +</div> +</section> +</section> +<section id="tips"> +<h3>TIPS<a class="headerlink" href="#tips" title="Permalink to this headline">¶</a></h3> +<p>If you want to map files <code class="docutils literal notranslate"><span class="pre">*.v</span></code> to SystemVerilog, add +<code class="docutils literal notranslate"><span class="pre">--langmap=SystemVerilog:.v</span></code> option.</p> +</section> +</section> +<section id="known-issues"> +<h2>KNOWN ISSUES<a class="headerlink" href="#known-issues" title="Permalink to this headline">¶</a></h2> +<p>See <a class="reference external" href="https://github.com/universal-ctags/ctags/issues/2674">https://github.com/universal-ctags/ctags/issues/2674</a> for more information.</p> +</section> +<section id="see-also"> +<h2>SEE ALSO<a class="headerlink" href="#see-also" title="Permalink to this headline">¶</a></h2> +<ul class="simple"> +<li><p><a class="reference internal" href="ctags.1.html#ctags-1"><span class="std std-ref">ctags(1)</span></a></p></li> +<li><p><a class="reference internal" href="ctags-client-tools.7.html#ctags-client-tools-7"><span class="std std-ref">ctags-client-tools(7)</span></a></p></li> +<li><dl class="simple"> +<dt>Language Reference Manuals (LRM)</dt><dd><ul> +<li><p>IEEE Standard for SystemVerilog — Unified Hardware Design, Specification, and +Verification Language, IEEE Std 1800-2017, +<a class="reference external" href="https://ieeexplore.ieee.org/document/8299595">https://ieeexplore.ieee.org/document/8299595</a></p></li> +<li><p>IEEE Standard for Verilog Hardware Description Language, IEEE Std 1364-2005, +<a class="reference external" href="https://ieeexplore.ieee.org/document/1620780">https://ieeexplore.ieee.org/document/1620780</a></p></li> +</ul> +</dd> +</dl> +</li> +</ul> +</section> +</section> + + + <div class="clearer"></div> + </div> + </div> + </div> + <div class="sphinxsidebar" role="navigation" aria-label="main navigation"> + <div class="sphinxsidebarwrapper"> + <h3><a href="../index.html">Table of Contents</a></h3> + <ul> +<li><a class="reference internal" href="#">ctags-lang-verilog</a><ul> +<li><a class="reference internal" href="#synopsis">SYNOPSIS</a></li> +<li><a class="reference internal" href="#description">DESCRIPTION</a><ul> +<li><a class="reference internal" href="#supported-kinds">Supported Kinds</a></li> +<li><a class="reference internal" href="#supported-language-specific-fields">Supported Language Specific Fields</a><ul> +<li><a class="reference internal" href="#parameter-field"><code class="docutils literal notranslate"><span class="pre">parameter</span></code> field</a></li> +</ul> +</li> +<li><a class="reference internal" href="#tips">TIPS</a></li> +</ul> +</li> +<li><a class="reference internal" href="#known-issues">KNOWN ISSUES</a></li> +<li><a class="reference internal" href="#see-also">SEE ALSO</a></li> +</ul> +</li> +</ul> + + <h4>Previous topic</h4> + <p class="topless"><a href="ctags-lang-python.7.html" + title="previous chapter">ctags-lang-python</a></p> + <h4>Next topic</h4> + <p class="topless"><a href="ctags-lang-inko.7.html" + title="next chapter">ctags-lang-inko</a></p> +<div id="searchbox" style="display: none" role="search"> + <h3 id="searchlabel">Quick search</h3> + <div class="searchformwrapper"> + <form class="search" action="../search.html" method="get"> + <input type="text" name="q" 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